The present invention relates to a metal interconnect, and, more specifically, to the microstructure of the metal interconnect layer.
The performance of a metal interconnect is affected by the microstructure. Microstructure, in turn, is affected by the anneal temperature. Increased anneal temperature in processing the metal interconnect layer leads to increased grain size, and increased grain size results in improved performance. That is, a grain boundary may be regarded as a defect in the grain that reduces electrical conductivity. Thus, the ideal metal interconnect microstructure is a single grain rather than a polycrystalline structure. In comparison to other grain boundaries, twin boundaries between grains are desirable for their increased mechanical strength and electrical conductivity. A polycrystalline structure in a metal interconnect layer typically contains less than 10% twin boundaries. Further, while elevated anneal temperatures are desirable for achieving large grains, the conventional annealing conditions for copper (Cu) back-end-of-line (BEOL) processing are 100° C. This is due to the coefficient of thermal expansion mismatch between Cu and its surrounding dielectric which leads to residual stress induced by the anneal process that can result in manufacturing and reliability concerns.